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The SAM contains circuitry specifically to assist in providing access to memory to the 6847 VDG. By simulating the VDG's memory access pattern in the SAM, only DA0 from the VDG need be connected (state transitions on this line then being enough information to advance the SAM's simulated counter). To do this accurately, the SAM can be told which mode the VDG has been set to. Usually, both chips will be configured to the same mode, but some extra modes can be produced by mismatching their configurations. The SAM data sheet documents some of these extra modes (Semigraphics 8, 12 and 24) but more are available, including some with non-visible bytes on each scanline.
The actual operation of the SAM's video address counter is fully described in the SAM block diagram (figure 4) and following text in the data sheet, but the combined behaviour of the two chips is only explicable when you know that at the end of each scanline, the VDG actually presents several more addresses before the falling edge of HS: ten more in 32-byte video modes, and six more in 16-byte modes.
Here's a trace of the VDG address lines relative to HS for one scanline in a 32-byte mode where you can see 42 addresses presented (41 transitions) before the falling edge of HS:
Thanks to Phill Harvey-Smith for capturing this trace.
While reading the data sheet, don't make the mistake (as I did for a long time!) of thinking that the X and Y divisors (figure 5) necessarily refer to the X and Y axes on-screen (though they do often enough to be distracting). Their place in the block diagram is accurate.
Updated 20 Jul 2007