Dragon hardware details

A quite incomplete document detailing how the Dragon is put together.

MC6809E 8-Bit Microprocessing Unit (MPU)

The chip that actually executes code. A very advanced 8-bit processor with an excellent set of addressing modes. The address bus is 16 bits wide, so it can directly address up to 64K. Although the data bus is 8 bits wide, there are many internal 16 bit operations possible, and all of the index registers are 16-bit, allowing them to directly point anywhere in address space.

Access to almost every device in the system by the MPU is determined by the SAM.

MC6883 (74LS783) Synchronous Address Multiplexer (SAM)

The SAM's primary job is to translate MPU requests for RAM into actual RAM addressing signals, transparently handling dynamic RAM refresh. Some blocking of address regions is made available with the S0-S2 outputs that allows easy connection of memory mapped I/O devices.

On an unexpanded Dragon 32, due to insufficient address decoding, writes to the upper 32K in map type 1 cause ROM and RAM to be selected simultaneously. This results in whatever would be in the ROM at that address to appear on the data bus while the RAM is selected for write, causing ROM data to be copied into RAM.

It also interleaves VDG RAM access to prevent contention. Rather than have a whole separate address bus for the VDG, the SAM has its own circuitry that emulates the access pattern of the VDG, needing only its DA0 line to drive it. Normally, the programmer will configure the SAM to reflect the configuration of the VDG, but mismatching them can produce some useful extra modes, as described in the SAM data sheet.

A 14.31818MHz crystal supplies a clock to the SAM, which divides that signal to provide clocks to other parts of the system (VDG and MPU). Some Dragon 64s (but not all) actually have a 14.218MHz crystal instead (Graheme Kinns speculates that this change was made to avoid harmonics that interfere with the video signal).

MC6847 Video Display Generator (VDG)

All data bus lines are connected through a latch to the main data bus. Additionally, the !A/S and INV lines are wired to D7 and D6 respectively so that 8-bit data in text mode also controls display of semigraphic characters and reverse video.

CSS, GM0, GM1, GM2 and !A/G are connected to bits 3-7 of the B side of PIA1. !INT/EXT is linked to GM0 to allow selection of semigraphics mode 6.

DA0 is the only address line used. It, together with !HS, is connected to the SAM which uses the signals to know where in the field the VDG is, and thus what data to address for it.

On NTSC Dragons, the main clock is supplied directly from the SAM's VCLK output (3.579MHz).

On PAL Dragon 64s, there is extra circuitry to disable supply of this clock at two points in every field: once 24 lines after the falling edge of FS (generated by the VDG itself), and again on its rising edge. In each case, these pauses last long enough to insert 25 non-VDG-generated scanlines (thus converting a 524-line nearly-NTSC signal to a 624-line nearly-PAL signal). As the VDG is stopped, horizontal sync interrupts are not passed on to the MPU during this 'padding'. An LM1889 is used to generate the chroma information.

PAL Dragon 32s seem to use a slightly different method of padding out the NTSC signal, as software analysis shows horizontal sync pulses appear to be generated for the whole frame. This may turn out to be specific to particular motherboard revisions.

Because no external character set generator is present, semigraphics mode 6 presents text characters as a vertically-repeating bit-pattern corresponding to what's on the data bus. This can give a limited form of high resolution graphics on the same screen as semigraphic characters. The effective limit (bearing in mind how !A/S and INV are connected) is that bit 6 will always visually be "off".

Because one of the bits used in semigraphics mode 6 to select colour is wired to the same data line used to turn on semigraphic characters, the Dragon is limited to two colours plus black in this mode with two colour sets selectable, instead of the four per colour set the VDG is technically capable of.

SAM-VDG interaction

As documented in the SAM data sheet, configuring the VDG for semigraphics mode 4 but the SAM for a mode that uses more memory produces some extra, higher vertical resolution, semigraphics modes. Experimentation shows that other interesting combinations are possible that offer more bytes-per-scanline than are actually displayed. There's some more discussion of the SAM-VDG interaction here.

PIA0: MC6821 Peripheral Interface Adaptor

Chip select lines are connected such that it is addressed at $FF00-$FF03.

PA0-PA6 usually act as inputs and are connected to the keyboard rows. PA0 and PA1 are also connected to the joystick firebuttons (Right and Left, respectively). Pressing a firebutton will ground the appropriate line.

PA7 is usually an input, and is connected to output of a comparator, one input of which is the output from the DAC connected to PIA1, the other input being selected from any of the four joystick axes. This allows the joystick positions to be determined by comparing their analogue input with successive outputs from the DAC.

All 8 lines of the B side (PB0-PB7) usually act as outputs and are connected both to the keyboard columns and the printer port's data lines (via a 74LS244 8-bit line driver).

CA1 and CB1 are connected to !HS and !FS from the VDG, and can be configured such that either a high-to-low transition or a low-to-high transition on either will generate an IRQ interrupt to the CPU.

CA2 and CB2 are used to select inputs on the analogue multiplexer.

PIA1: MC6821 Peripheral Interface Adaptor

Chip select lines are connected such that it is addressed at $FF20-$FF23.

PA0 represents a single-bit input from the cassette port. PA1 is connected to the parallel port's STROBE line.

PA2-PA7 will generally be used as outputs and connect directly to a DAC (the output of which can be selected for audio output, and used to compare against joystick inputs (see PIA0, PA7).

PB0 connects to the parallel port's !BUSY line. PB1 as an output provides a single-bit sound source independent of the analogue multiplexer.

PB2 selects between two ROMs on Dragon 64s (one being the Dragon 32 compatible ROM, the other being the ROM that gets copied to high RAM in 64K mode). The Dragon 32 ROM checks this line and configures the SAM to address 16K of RAM if it is tied high - perhaps a 16K model was originally planned?

PB3-PB7 are connected to the CSS, GM0, GM1, GM2 and !A/G lines of the VDG respectively.

CA1 is connected to the parallel port's ACK line, and CB1 to the cartridge port's detection line. These can be configured to generate FIRQ interrupts.

CA2 controls the cassette motor and CB2 enables the analogue audio output from side Y of the analogue multiplexer.

MC14529 Analogue multiplexer

This provides 2 analogue input switches used to select joystick axes and audio sources. Each has four possible inputs, selected by CA2 (bit 0) and CB2 (bit 1) of PIA0. Only having one set of selection inputs means that when you switch an audio source (side Y), you also switch the joystick axis (side X) and vice-versa.

Side X is permanently enabled, and selects one of the four joystick axes to be an input to the comparator (the output of which can be read on PA7 of PIA0).

Side Y is enabled by setting CB2 on PIA1, and selects from three different audio sources (the fourth is unconnected): output from the DAC connected to PIA1, the cassette port input or the FSND line from the cartridge port.

The sound sources to the analogue mux are switched to the sound bus. This is shared with the single-bit sound source (PIA1 PB1). The way this line is configured affects the output voltage. Here are some measurements from a Dragon 64 with the PIA line as an input, and as an output; high and low.

Output (low)0.18V3.02V1.80+/-0.20V0.00V
Output (high)1.30V4.70V2.60+/-0.25V3.90V

Updated 15 Mar 2013