Sock's GIME register reference

People keep looking for GIME information, but it seems that there is no place you can find it on the web. So, I've decided to try to put together some GIME data so CoCo programmers could put it to good use.

The GIME is a custom chip designed to replace a number of parts from the CoCo 1&2 and also add extra CoCo 3 specific features. For now, at least, I'll concentrate mostly on CoCo 3 features. The CoCo 1&2 features work the same as before, so you can probably find that information on other web sites.

FF90 (65424) Initialization Register 0 - INIT0

Bit 7COCO1=CoCo 1/2 compatible mode
Bit 6MMUEN1=MMU enabled
Bit 5IEN1=GIME chip IRQ enabled
Bit 4FEN1=GIME chip FIRQ enabled
Bit 3MC31=RAM at FExx is constant
(secondary vectors)
Bit 2MC21=standard SCS
(spare chip select)
Bits 1-0MC1
ROM map control
0x=16K internal, 16K external
10=32K internal
11=32K external (except interrupt vectors)

To use CoCo 3 graphics, the COCO bit must be set to zero. When using CoCo 1/2 resolutions, the bit is set to 1. RSDOS typically sets the INIT0 register to 196 in CoCo 2 resolutions and 68 when using CoCo 3 graphics modes.

FF91 (65425) Initialization Register 1 - INIT1

Bit 7Unused
Bit 6?Memory type
1=256K, 0=64K chips
Bit 5TINSTimer clock source
1=279.365 nsec, 0=63.695 usec
Bits 4-1Unused
Bit 0TRMMU task select
1=enable FFA8-FFAF MMU registers
0=enable FFA0-FFA7 MMU registers

The TINS bit selects the clock speed of the countdown timer. The 279 ns clock is useful for interrupt driven sound routines while the 63 us clock is used for a slower timer. The task bit is generally set to zero in DECB.
The task register select which set of MMU bank registers to assign to the CPU's 64K workspace.

FF92 (65426) Interrupt request enable register - IRQENR

Bits 7-6Unused
Bit 5TMR1=Enable timer IRQ
Bit 4HBORD1=Enable Horizontal border IRQ
Bit 3VBORD1=Enable Vertical border IRQ
Bit 2EI21=Enable Serial data IRQ
Bit 1EI11=Enable Keyboard IRQ
Bit 0EI01=Enable Cartridge IRQ

TMR: An interrupt is generated whenever the 12 bit timer counts down to zero.
HBORD: A horizontal border interrupt is generated on the falling edge of HSYNC.
VBORD: A vertical border interrupt is generated on the falling edge of VSYNC.
EI2: A serial interrupt is generated on the falling edge of the signal on PIN 4 of the serial port.
EI1: A keyboard interrupt is generated whenever a zero appears on any one of PA0-PA6 on the PIA0.
EI0: A cartridge interrupt is generated on the falling edge of the signal on PIN 8 of the cartridge port.
Reading from the register tells you which interrupts came in and acknowledges and resets the interrupt source.

FF93 (65427) Fast interrupt request enable register - FIRQENR

Bits 7-6Unused
Bit 5TMR1=Enable timer FIRQ
Bit 4HBORD1=Enable Horizontal border FIRQ
Bit 3VBORD1=Enable Vertical border FIRQ
Bit 2EI21=Enable Serial data FIRQ
Bit 1EI11=Enable Keyboard FIRQ
Bit 0EI01=Enable Cartridge FIRQ

This register works the same as IRQENR except that it generates FIRQ interrupts.

Here's a table of the interrupt vectors and where they end up going. You can't change the $FFxx vectors, but you can change the $FExx and $01xx vectors which contain jmps/lbras to the interrupt routine.
InterruptCPU readswhich points towhich jumps to
this routine

FF94 (65428) Timer register MSB

Bits 7-4Unused
Bits 3-0TMRHTimer bits 8-11

FF95 (65429) Timer register LSB

Bits 7-0TMRLTimer bits 0-7

The 12 bit timer can be loaded with any number from 0-4095. The timer resets and restarts counting down as soon as a number is written to FF94. Writing to FF95 does not restart the timer, but the value does save. Reading from either register does not restart the timer. When the timer reaches zero, it automatically restarts and triggers an interrupt (if enabled). The timer also controls the rate of blinking text.
Storing a zero to both registers stops the timer from operating. Lastly, the timer works slightly differently on both 1986 and 1987 versions of the GIME. Neither can actually run a clock count of 1. That is, if you store a 1 into the timer register, the 1986 GIME actually processes this as a '3' and the 1987 GIME processes it as a '2'. All other values stored are affected the same way : nnn+2 for 1986 GIME and nnn+1 for 1987 GIME.

FF96 (65430) Reserved

Bits 7-0Unused

FF97 (65431) Reserved

Bits 7-0Unused

FF98 (65432) Video mode register - VMODE

Bit 7BP1=Graphics modes
0=Text modes
Bit 6Unused
Bit 5BPI1=Composite color phase invert
Bit 4MOCH1=Monochrome on Composite video out
Bit 3H501=50Hz video
0=60Hz video
Bits 2-0LPR00x=one line per row
010=two lines per row
011=eight lines per row
100=nine lines per row
101=ten lines per row
110=eleven lines per row
111=*infinite lines per row

*Mostly useless, but it does generate a graphics mode where the whole screen is filled with the same line of graphics - like a 320x1 resolution. This can be used for a very fast oscilloscope type display where the program only updates data in one scan line over time and as the screen refreshes, you get a screen full of samples. I also used it in my Boink bouncing ball demo to take manual control of the vertical resolution of the screen to make the ball appear that it's going up and down (without actually scrolling the whole screen up and down).

FF99 (65433) Video resolution register - VRES

Bit 7Unused?
Bits 6-5LPF00=192 scan lines on screen
01=200 scan lines on screen
10=*zero/infinite lines on screen (undefined)
11=225 scan lines on screen
Bits 4-2HRESHorizontal resolution using graphics:
000=16 bytes per row
001=20 bytes per row
010=32 bytes per row
011=40 bytes per row
100=64 bytes per row
101=80 bytes per row
110=128 bytes per row
111=160 bytes per row

When using text:
0x0=32 characters per row
0x1=40 characters per row
1x0=64 characters per row
1x1=80 characters per row
Bits 1-0CRESColor Resolution using graphics:
00=2 colors (8 pixels per byte)
01=4 colors (4 pixels per byte)
10=16 colors (2 pixels per byte)
11=Undefined (would have been 256 colors)

When using text:
x0=No color attributes
x1=Color attributes enabled

*The zero/infinite scanlines setting will either set the screen to display nothing but border (zero lines) or graphics going all the way up and down out of the screen, never retriggering. It all depends on when you set the register. If you set it while the video raster was drawing the vertical border you get zero lines, and if you set it while video was drawing graphics you get infinite lines. Mostly useless, but it should be possible to coax a vertical overscan mode using this with some tricky timing.

HRESCRESCommonly used graphics modes
11101640 pixels, 4 colors
10100640 pixels, 2 colors
11001512 pixels, 4 colors
10000512 pixels, 2 colors
11110320 pixels, 16 colors
10101320 pixels, 4 colors
01100320 pixels, 2 colors
11010256 pixels, 16 colors
10001256 pixels, 4 colors
01000256 pixels, 2 colors
10110160 pixels, 16 colors
01101160 pixels, 4 colors
00100160 pixels, 2 colors
10010128 pixels, 16 colors
01001128 pixels, 4 colors
00000128 pixels, 2 colors

FF9A (65434) Border color register - BRDR

Bits 7-6Unused
Bits 5-0BRDRBorder color

This controls the color of the border around the screen. The color bits work the same as the palette registers. This register only controls the border color of CoCo 3 video modes and does not affect Coco 1/2 modes.

FF9B (65435) Reserved

Bits 7-2Unused
Bits 1-0VBANKUsed by Disto 2 Meg upgrades to switch video between 512K banks

FF9C (65436) Vertical scroll register - VSC

Bits 7-4Unused
Bits 3-0VSCVertical smooth scroll.

The vertical scroll register is used to allow smooth scrolling in text modes. Consecutive numbers scroll the screen upwards one scan line at a time in video modes where more than one scan line makes up a row of text (typically 8 lines per character row) or graphics (double height+ graphics).

FF9D (65437) Vertical offset register MSB

Bits 7-0Y15-Y8MSB Start of video in RAM
(video location * 2048)

FF9E (65438) Vertical offset register LSB

Bits 7-0Y7-Y0LSB Start of video in RAM
(video location * 8)

Y15-Y0 is used to set the video mode to start in any memory location in 512K by steps of 8 bytes. On a 128K machine, the memory range is $60000-$7FFFF. There is a bug in some versions of the GIME that causes the computer to crash when you set odd numbered values in FF9E in some resolutions, so it's safest to limit positioning to steps of 16 bytes. Fortunately, you can use FF9F to make up for it and get steps as small as 2 bytes.

FF9F (65439) Horizontal offset register

Bit 7HVEN1=Horizontal virtual screen enable (256 bytes per row)
0=Normal horizontal display
Bits 6-0X6-X0Horizontal offset address
(video location *2)

You can combine the horintal and vertical offsets to get a higher definition video position: Y15-Y4,X6-X0 which gives you 19 bit positioning by steps of 2 bytes.
Otherwise, you can use this register to do scrolling effects. The virtual screen mode allows you to set up a 256 byte wide graphics or text screen, showing only part of it at a time and allowing you to scroll it vertically.

FFA0-FFA7 (65440-65447) MMU bank registers (task one)

FFA0Bank at $0000-$1FFF
FFA1Bank at $2000-$3FFF
FFA2Bank at $4000-$5FFF
FFA3Bank at $6000-$7FFF
FFA4Bank at $8000-$9FFF
FFA5Bank at $A000-$BFFF
FFA6Bank at $C000-$DFFF
FFA7Bank at $E000-$FFFF
(or $E000-$FDFF if secondary vectors enabled)

These MMU registers are enabled when the task bit (FF91) is clear. These MMU registers allocate chunks of 8K into the CPU's 64K workspace. Valid bank ranges are 56-63 on 128K machines, 0-63 on 512K machines, 0-127 on 1Meg machines and 0-255 on 2Meg machines.
These registers can be read, but the upper 2 bits must be masked out as they return bleedover from the bus (sometimes zero, sometimes one). This is okay for machines with 512K or less, but poses a problem for 1Meg and up. Supposedly some memory upgrades fixed this, but most don't so you can't rely on those 2 bits to be there when you read the registers.

FFA8-FFAF (65448-65455) MMU bank registers (task two)

FFA8Bank at $0000-$1FFF
FFA9Bank at $2000-$3FFF
FFAABank at $4000-$5FFF
FFABBank at $6000-$7FFF
FFACBank at $8000-$9FFF
FFADBank at $A000-$BFFF
FFAEBank at $C000-$DFFF
FFAFBank at $E000-$FFFF
(or $E000-$FDFF if secondary vectors enabled)

These MMU registers are enabled when the task bit (FF91) is set. These are primarily used by the operating system.

FFB0-FFBF (65456-65471) Color palette registers

FFB0Color 0Bits 7-6 Unused
Bit 5 = High order Red
Bit 4 = High order Green
Bit 3 = High order Blue
Bit 2 = Low order Red
Bit 1 = Low order Green
Bit 0 = Low order Blue
FFB1Color 1same as above
FFB2Color 2...
FFB3Color 3
FFB4Color 4
FFB5Color 5
FFB6Color 6
FFB7Color 7
FFB8Color 8
FFB9Color 9
FFBAColor 10
FFBBColor 11
FFBCColor 12
FFBDColor 13
FFBEColor 14
FFBFColor 15

The color set when using composite monitors is different than above (which applies to RGB monitors). On composite displays, Bits 5-4 control 4 levels of intensity, and bits 3-0 control 16 hues of color.

These registers can also be read to determine what palettes are set but like the MMU registers, the upper 2 bits must be masked out. Both reading and writing to the palette registers causes a small 'glitch' on the screen. If you want to avoid them, you can change the palettes while the video is in the vertical or horizontal border.
On the other hand, you could also generate the glitches on purpose, to superimpose snow on the screen. The glitches appear as the color you set the register to (with a bit of the previous color setting at the beginning) and with precise CPU timing loops you could actually superimpose definable graphics over the screen this way.

FFD8/FFD9 (65496/65497) CPU clock rate

FFD8'Slow poke'Any write selects 0.89 Mhz CPU clock
FFD9'Fast poke'Any write selects 1.79 Mhz CPU clock

FFDE/FFDF (65502/65503) ROM/RAM map type

FFDEROM modeAny write switches system ROMs into memory map
FFDFRAM modeAny write selects all-RAM mode

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